As an approach to meet increasing demand for smaller and higher performance computing device, there has been an exploration of three dimensional (3D) or stacked fabrication of circuit devices. In particular, there has been research on stacking memory devices to increase storage capacity in smaller footprints and provide higher performance. Traditional processing techniques require a minimum amount of size for circuit devices limited by the amount of real estate required to implement the circuit elements. Traditional practice in stacked circuits has been to create a conductor to contact a channel through a deck of circuit elements by depositing the conductor, and then isolate specific contacts by CMP (chemical mechanical processing).
Current CMP results in undesired processing artifacts. A processing artifact refers to an imperfection in the circuit resulting from the processing. Thus, evidence of over-etching, over-ablation, scratching from polishing, thinning of a separation layer, or other evidence can be referred to as a processing artifact. In addition to processing artifacts created by the circuit processing, the chemicals and processes needed are dependent on the material used as the conductor layer. Currently finding a good chemical process to provide good contact isolation is challenging, in addition to the leaving of processing artifacts. Such challenges currently extend the time needed to process the circuits, and increase the cost of the processing. The relatively high cost and time requirements limit the commercial viability for high volume manufacturing.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.